1 m e m o r y all data sheets are subject to change without notice (858) 503-3300 - fax: (858) 503-3301 - www.maxwell.com 4 megabit (512k x 8-bit) sram 32c408b ?2002 maxwell technologies all rights reserved. 05.02.02 rev 7 f eatures : ? 512k x 8-bit cmos architecture r ad -p ak ? technology hardened against natural space radi- ation total dose hardness: - > 100 krad (si), depending upon space mission single event effect: - sel th : > 68 mev/mg/cm 2 - seu th : < 3mev/mg/cm 2 - seu saturated cross section: 6e-9 cm 2 /bit package: -36 pin r ad -p ak ? flat pack fast propagation time: -20, 25, 30 ns maximum access time single 5v + 10% power supply low power dissipation: - standby: 60ma (ttl); 10ma (cmos) - operating: 180 ma (20 ns); 170 ma (25 ns); 160 ma (30 ns) ttl compatible inputs and outputs fully static operation - no clock or refresh required three state outputs d escription : maxwell technologies? 32c408b high-speed 4 megabit sram microcircuit features a greater than 100 krad (si) total dose tolerance, depending upon space mission. using r ad -p ak ? packaging technology, the 32c408b realizes higher density, higher performance and lower power consumption, and is well suited for high-speed system application. its fully static design eliminates the need for external clocks, while the cmos cir- cuitry reduces power consum ption and provides higher reli- ability. the 32c408b is equipped with eight common input/ output lines, chip select and output enable, allowing for greater system flexibility and eliminating bus contention. maxwell technologies' patented r ad -p ak packaging technol- ogy incorporates radiation shielding in the microcircuit pack- age. in a geo orbit, r ad -p ak can provides true greater than 100 krad (si) total radiation dose tolerance; dependent upon space mission. the patented radiation-hardened r ad -p ak technology incorporates radiation shielding in the microcircuit package. it eliminates the need for box shielding while provid- ing the required radiation shielding for a lifetime in orbit or a space mission. this product is available with packaging and screening up to class s. nc a18 a0 a1 a2 a3 a4 cs i/o1 i/o2 vcc vss i/o3 i/o4 we a5 a6 a7 a8 a9 a17 a16 a15 oe i/o8 i/o7 vss vcc a14 a13 a12 a11 nc a10 i/o5 i/o6 1 36 18 19 row decoder input data control memory matrix 1024 rows x 4096 columns column i/o column decoder cs a13 a0 a1 a3 dq0 dq7 dq0 dq7 a14 a15 a16 a17 a18 a2 a12 a11 a10 a9 a8 a7 a6 a5 a4 we oe 32c408b logic diagram
m e m o r y 2 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. 4 megabit (512k x 8-bit) sram 32c408b 05.02.02 rev 7 t able 1. 32c408b a bsolute m aximum r atings p arameter s ymbol m in m ax u nit voltage on any pin relative to v ss v in , v out -0.5 v cc +0.5 v voltage on v cc supply relative to v ss v cc -0.5 7.0 v power dissipation p d -- 1.0 w storage temperature t s -65 +150 c operating temperature t a -55 +125 c t able 2. 32c408b r ecommended o perating c onditions p arameter s ymbol m in m ax u nit supply voltage v cc 4.5 5.5 v ground v ss 00v input high voltage 1 1. v ih (max) = v cc + 2.0v ac(pulse width < 10ns) for i < 20ma. v ih 2.2 v cc +0.5 v input low voltage 2 2. v il (min) = -2.0v ac(pulse width < 10ns) for i < 20ma. v il -0.5 0.8 v thermal impedance jc -- 0.63 c/w t able 3. 32c408b dc e lectrical c haracteristics (v cc =5v +/- 10%, t a = -55 to +1?25c, u nless o terwise s pecified p arameter c ondition s ymbol s ubgroups m in t yp m ax u nit input leakage current v in = v ss to v cc i li 1, 2, 3 -2 -- 2 a output leakage current cs =v ih or oe =v ih or we =v il , v out =v ss to v cc i lo 1, 2, 3 -2 -- 2 a output low voltage i ol = 8ma v ol 1, 2, 3 -- -- 0.4 v output high voltage i oh = -4ma v oh 1, 2, 3 2.4 -- v average operating cur- rent -20 -25 -30 min cycle, 100% duty, cs =v il , i out =0ma, v in = v ih or v il i cc 1, 2, 3 -- -- -- -- 180 170 160 ma standby power supply current cs = v ih i sb 1, 2, 3 -- -- 60 ma f = 0mhz, cs > v cc - 02v, v in > v cc - 0.2v or v in < 0.2v i sb1 1, 2, 3 -- -- 10 input capacitance 1 1. guaranteed by design v in = 0v, f = 1mhz, t a = 25 c. c in 1, 2, 3 -- -- 7 pf output capacitance 1 v i/o = 0v c i/o 1, 2, 3 -- -- 8 pf
m e m o r y 3 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. 4 megabit (512k x 8-bit) sram 32c408b 05.02.02 rev 7 t able 4. 32c408b ac c haracteristics for r ead c ycle (v cc =5v +/- 10%, t a = -55 to +1?25c, u nless o terwise s pecified p arameter s ymbol s ubgroups m in t yp m ax u nit read cycle time -20 -25 -30 t rc 9, 10, 11 20 25 30 -- -- -- -- -- -- ns address access time -20 -25 -30 t aa 9, 10, 11 -- -- -- -- -- -- 20 25 30 ns chip select access time -20 -25 -30 t co 9, 10, 11 -- -- -- -- -- -- 20 25 30 ns output enable to output valid -20 -25 -30 t oe 9, 10, 11 -- -- -- -- -- -- 10 12 14 ns chip select to output in low-z -20 -25 -30 t lz 9, 10, 11 -- -- -- 3 3 3 -- -- -- ns output enable to output in low-z -20 -25 -30 t olz 9, 10, 11 -- -- -- 0 0 0 -- -- -- ns chip deselect to output in high-z -20 -25 -30 t hz 9, 10, 11 -- -- -- 5 6 8 -- -- -- ns output disable to output in high-z -20 -25 -30 t ohz 9, 10, 11 -- -- -- 5 6 8 -- -- -- ns output hold from address change -20 -25 -30 t oh 9, 10, 11 3 5 5 -- -- -- -- -- -- ns chip select to power up time -20 -25 -30 t pu 9, 10, 11 -- -- -- 0 0 0 -- -- -- ns chip select to power down time -20 -25 -30 t pd 9, 10, 11 -- -- -- 10 15 20 -- -- -- ns
m e m o r y 4 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. 4 megabit (512k x 8-bit) sram 32c408b 05.02.02 rev 7 t able 5. 32408b f unctional d escription 1 1. x = don?t care. cs we oe m ode i/o p in s upply c urrent h x x not select high-z i sb , i sb1 l h h output disable high-z i cc l h l read d out i cc llxwrited in i cc t able 6. 32c408b ac c haracteristics for w rite c ycle (v cc =5v +/- 10%, t a = -55 to +1?25c, u nless o terwise s pecified p arameter s ymbol s ubgroups m in t yp m ax u nit write cycle time -20 -25 -30 t wc 9, 10, 11 20 25 30 -- -- -- -- -- -- ns chip select to end of write -20 -25 -30 t cw 9, 10, 11 14 15 17 -- -- -- -- -- -- ns address setup time -20 -25 -30 t as 9, 10, 11 0 0 0 -- -- -- -- -- -- ns address valid to end of write -20 -25 -30 t aw 9, 10, 11 14 15 17 -- -- -- -- -- -- ns write pulse width (oe high) -20 -25 -30 t wp 9, 10, 11 14 15 17 -- -- -- -- -- -- ns write recovery time -20 -25 -30 t wr 9, 10, 11 0 0 0 -- -- -- -- -- -- ns write to output in high-z -20 -25 -30 t whz 9, 10, 11 -- -- -- 5 5 6 -- -- -- ns
m e m o r y 5 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. 4 megabit (512k x 8-bit) sram 32c408b 05.02.02 rev 7 f igure 1. t iming w aveform of w rite c ycle (1) (oe c lock ) write pulse width(oe low) -20 -25 -30 t wp1 9, 10, 11 -- -- -- 20 25 30 -- -- -- ns data to write time overlap -20 -25 -30 t dw 9, 10, 11 9 10 11 -- -- -- -- -- -- ns end write to output low-z 1 -20 -25 -30 tow 9, 10, 11 -- -- -- 6 7 8 -- -- -- ns data hold from write time -20 -25 -30 t dh 9, 10, 11 0 0 0 -- -- -- -- -- -- ns t able 6. 32c408b ac c haracteristics for w rite c ycle (v cc =5v +/- 10%, t a = -55 to +1?25c, u nless o terwise s pecified p arameter s ymbol s ubgroups m in t yp m ax u nit
m e m o r y 6 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. 4 megabit (512k x 8-bit) sram 32c408b 05.02.02 rev 7 f igure 2. t iming w aveform of w rite c ycle (oe l ow f ixed ) 1. all write cycle timing is referenced from the la st valid address to the first transition address. 2. a write occurs during the overlap of a low cs and a low we . a write begins at the latest transition among cs going low and we going low: a write ends at the earliest transition among cs going high or we going high. t wp is measured from beginning of write to end of write. 3. t cw is measured from the later of cs going low to end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. twr applied in case a write ends as cs or we going high. 6. if oe , cs and we are in the read mode during this period, the i/o pins are in the output low-z state. inputs of opposite phase of the output must not be applied because bus contention can occur. 7. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. ic cs goes low simultaneously with we going low or after we going low, the outputs remain high impedance state. 9. d out is the read data of the new address. 10.when cs is low: i/o pins are in the output state. the input signals in the opposite phase leading to the output should not be applied. f igure 3. t iming w aveform of r ead c ycle (1) (a ddress c ontrolled , cs = oe = v il , we = v ih )
m e m o r y 7 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. 4 megabit (512k x 8-bit) sram 32c408b 05.02.02 rev 7 f igure 4. t iming w aveform of r ead c ycle (2) (we = v ih ) 1. we is high for read cycle. 2. all read cycle timing is referenced from the la st valid address to the first transition address. 3. t hz and t ohz are defined as the time at which the outputs achiev e the open circuit condition and are not referenced to v oh or v ol levels. 4. at any given temperature and voltage condition, t hz(max) is less than t lz(min) both for a given device and from device to device. 5. transition is measured +200mv from steady state voltage wi th load(b). this parameter is sampled and not 100% tested. 6. device is continuously selected with cs = v il . 7. address valid prior to coincident with cs transition low. 8. for common i/o applications, minimi zation or elimination of bus contention is necessary during read and write cycle. f igure 5. sram h eavy i on c ross s ection
m e m o r y 8 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. 4 megabit (512k x 8-bit) sram 32c408b 05.02.02 rev 7 f igure 6. sram p roton seu c ross s ection s tatic
m e m o r y 9 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. 4 megabit (512k x 8-bit) sram 32c408b 05.02.02 rev 7 f36-01 note: all dimensions in inches 36 p in f lat r ad -p ak ? p ackage s ymbol d imension m in n om m ax a 0.122 0.135 0.148 b 0.015 0.017 0.019 c 0.008 0.010 0.012 d -- 0.930 0.940 e 0.638 0.645 0.652 e1 -- -- 0.690 e2 0.560 0.565 -- e3 0.005 0.040 -- e 0.050 bsc l 0.390 0.400 0.410 q 0.088 0.098 0.108 s1 0.005 0.032 -- n36
m e m o r y 10 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. 4 megabit (512k x 8-bit) sram 32c408b 05.02.02 rev 7 important notice: these data sheets are created using the chip manufacturers published specifications. maxwell technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. the specifications presented within these data sheets represent the latest and most accurate information available to date. however, these specifications are subject to change without notice and maxwell technologies assumes no responsibility for the use of this information. maxwell technologies? products are not authorized for use as critical components in life support devices or systems without express written approval from maxwell technologies. any claim against maxwell technologies must be made within 90 days from the date of shipment from maxwell tech- nologies. maxwell technologies? liability shall be limited to replacement of defective parts.
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